The present invention relates to a winner-take-all (WTA) analog circuit, and more particularly, to a WTA circuit wherein the number of prominent elements selected can be chosen.
Artificial neural networks and fuzzy logic are very effective in processing complex scientific, and engineering problems such as pattern classification since both of them are non-parametric, and need no mathematical model. Their massive parallelism, learning ability, adaptivity, and fault tolerance make them more attractive in the field of pattern information processing. Although software simulations based on theory of artificial neural networks, and fuzzy logic paradigms can be performed in conventional Von Neumann machines, the simulations usually take too much time for practical applications. Recently many significant advances in electronic implementation of neural networks, and fuzzy logic have been achieved. Winner-take-all networks for selecting the most prominent one from N elements are central processing components in most models of neural networks such as Hamming neural network, ART (Adaptive Resonance Theory) model, SOFM (Self-organized Feature Mapping) model, and fuzzy processors. It can be regarded as 1-WTA if only one prominent element is selected at one time, we call it k-WTA networks if it can select k maximum from N elements.
The WTA networks are mainly implemented with analog circuits since WTA functions are nonlinear, and can make full use of the nonlinearity of analog circuits. There are two modes to implement WTA with analog circuits, current mode and voltage mode. Two kinds of complexity will exist according to wire length, and the number of transistors used in the WTA circuits, one is linearly proportional to the number of input elements, and the other is quadratic.
k-WTA is very useful in pattern classification such as k-nearest neighbor classifier, Hamming neural classifier, and some cascaded classification systems, since one classifier can not achieve very high performance, however, if a small set of candidates can be provided, for example k(k less than  less than N), then a simple classifier with small complementary feature sets can be cascaded to realize multi-stage classification. A k-WTA network is necessary to implement this function. Several WTA circuits have been reported in the literatures. Most of them however can only realize the 1-WTA function having a complexity of O(N2). This high complexity can make them difficult to implement when they process a large number of input elements in the network. Further many of these WTA circuits need an applied bias current, so that the range of inputs is limited.
It is therefore the object of the present invention to provide a k-WTA analog circuit wherein k maximum from N elements can be selected. The WTA analog circuit disclosed herein provides for a plurality of inputs and outputs. Each input, its corresponding output, and associated circuitry serve to form stages within the circuit. Therefore the circuit has the advantage of expandability, as the scale of the k-WTA circuit can be easily expanded by adding further stages. The inputs can also be weighted. The present invention has a further advantage of being self-adaptive, as it needs no externally applied bias current, voltage, or clock signals. This allows for a large dynamic range of input currents.
It is a further objective of the present invention to provide a k-WTA circuit that is easily reconfigurable as 1-WTA, 2-WTA, or 3-WTA. In the invention as disclosed the circuit can be reconfigured as seen in one embodiment through the use of external select-inputs which can be logical voltage levels. In the preferred embodiment if the select-inputs are both low logic levels then the circuit is configured as 1-WTA This means that only one input with a maximum-value is selected with its corresponding output. If either of the select-inputs is high and the other is low then the circuit is configured as 2-WTA and 2 current inputs with maximum values are selected with their corresponding outputs. If both select-inputs are high then the circuit is configured as 3-WTA and 3 current inputs with maximum values are selected with their corresponding outputs.